1. Field of the Invention
The present invention provides a semiconductor structure, and more particularly, to a semiconductor structure in which the bump pitch is narrower than the bump width.
2. Descriptions of the Related Art
With the advancement of semiconductor packaging technologies, the conventional practice of using bonding wires for electrical connection has been replaced by the use of bumps. By disposing bumps on a chip through electroplating, solder paste transferring, evaporation or direct adhesion of soldering balls, electrical connection between the chip and substrate circuit can be accomplished. Among various bump-related packaging technologies, the Flip Chip in Package (FCiP) technology has become the mainstream technology over recent years due to the considerations of the cost and the package size.
According to FCiP technology, a chip is disposed upside down so that the bumps on the chip can be electrically connected with a circuit on the substrate directly. To increase the circuit density on individual packages, an active surface of the chip must be made to have as many bump contacts as possible, which necessitates the reduction of the bump pitch and the bump width. However, the bump pitch and the bump width can only be reduced to a limited extent, and a small bump pitch also leads to a reduced bump width. When probes are used for inspection, the small bumps make it necessary to operate the probes at a high precision, which increases the time duration, cost and difficulty of the inspection process.
FIGS. 1A and 1B illustrate the top and cross-sectional view of a conventional semiconductor structure 1. In detail, the semiconductor structure 1 comprises a substrate 10, a plurality of connection pads 12, a protection layer 14, a plurality of under bump metallization (UBM) layers 16 and a plurality of bumps 18. The connection pads 12 are disposed on the substrate 10 adjacent to each other and disposed in sequence. The connection pads 12 are electrically connected to both the UBM layers 16 and the bumps 18 via a plurality of openings 142 defined in the protection layers 14. As shown, in conventional circuit designs, the bump pitch W1 must be wider than the bump width W2 to prevent short-circuiting due to the contaction between the bumps. In other words, while designing the bump size, the limitation of the bump width W2 (should be narrower than the bump pitch W1) is considered. To reduce the overall size, the limitation of the bump width has impeded testing; for example, the positioning accuracy of the probes is limited, and bumps with an insufficient width will increase the difficulty in packaging and increase the probability of bump exfoliation.
Accordingly, it is important to provide a semiconductor structure that can overcome the aforesaid shortcomings, have a small package size and a high circuit density, and allows for easy electrical testing.